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4Y1

3Y1

GND

2Y1

1Y1

NC

A1

GND

NC

A2

GND

NC

A3

NC

A4

GND

CLK

OE1

OE2

SEL

GND

A5

A6

A7

NC

GND

A8

NC

GND

A9

NC

4Y9

3Y9

GND

2Y9

1Y9

1Y2

2Y2

GND

3Y2

4Y2

1Y3

2Y3

GND

3Y3

4Y3

GND

1Y4

2Y4

3Y4

4Y4

GND

1Y5

2Y5

3Y5

4Y5

GND

1Y6

2Y6

3Y6

4Y6

GND

1Y7

2Y7

GND

3Y7

4Y7

1Y8

2Y8

GND

3Y8

4Y8

NC − No internal connection

SN74ALVCH16831

1-TO-4 ADDRESS REGISTER/DRIVER

WITH 3-STATE OUTPUTS

SCES083F – AUGUST 1996 – REVISED SEPTEMBER 2004

•

Member of the Texas Instruments Widebus™

Family

•

Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

•

Latch-Up Performance Exceeds 250 mA Per

JESD 17

•

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

This 1-bit to 4-bit address register/driver is designed

for use in applications in which a single address bus

is driving four separate memory locations. The

SN74ALVCH16831 can be used as a buffer or a

register, depending on the logic level of the select

(SEL) input.

When SEL is logic high, the device is in the buffer

mode. The outputs

follow

the

inputs

and

are

controlled by the two output-enable (OE) controls.

Each OE controls two groups of nine outputs.

When SEL is logic low, the device is in the register

mode. The register is an edge-triggered D-type

flip-flop. On the positive transition of the clock (CLK)

input, data set up at the A inputs is stored in the

internal registers. OE controls operate the same as in

buffer mode.

When OE is logic low, the outputs are in a normal

logic state (high or low logic level). When OE is logic

high, the outputs are in the high-impedance state.

SEL and OE do not affect the internal operation of

the flip-flops. Old data can be retained or new data

can be entered while the outputs are in the

high-impedance state.

To ensure the high-impedance state during power up

pullup resistor; the minimum value of the resistor is

determined by the current-sinking capability of the

driver.

Active bus-hold circuitry holds unused or undriven

inputs at a valid logic state. Use of pullup or pulldown

resistors

with

the

bus-hold

circuitry

is

not

recommended.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 1996–2004, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.