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TLC2652AC8D 데이터시트(PDF) 2 Page - Texas Instruments |
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TLC2652AC8D 데이터시트(HTML) 2 Page - Texas Instruments |
2 / 31 page TLC2652, TLC2652A, TLC2652Y Advanced LinCMOS ™ PRECISION CHOPPER-STABILIZED OPERATIONAL AMPLIFIERS SLOS019C – SEPTEMBER 1988 – REVISED FEBRUARY 1999 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) Innovative circuit techniques are used on the TLC2652 and TLC2652A to allow exceptionally fast overload recovery time. If desired, an output clamp pin is available to reduce the recovery time even further. The device inputs and output are designed to withstand – 100-mA surge currents without sustaining latch-up. Additionally the TLC2652 and TLC2652A incorporate internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as exposure to ESD may result in degradation of the device parametric performance. The C-suffix devices are characterized for operation from 0 °C to 70°C. The I-suffix devices are characterized for operation from – 40 °C to 85°C. The Q-suffix devices are characterized for operation from –40°C to125°C. The M-suffix devices are characterized for operation over the full military temperature range of – 55 °C to125°C. AVAILABLE OPTIONS PACKAGED DEVICES VIOmax 8 PIN 14 PIN 20 PIN CHIP TA VIOmax AT 25 °C SMALL OUTLINE (D008) CERAMIC DIP (JG) PLASTIC DIP (P) SMALL OUTLINE (D014) CERAMIC DIP (J) PLASTIC DIP (N) CHIP CARRIER (FK) FORM (Y) 0 °C 1 µV TLC2652AC 8D TLC2652ACP TLC2652AC 14D TLC2652ACN to 1 µV 3 µV TLC2652AC-8D TLC2652C-8D — — TLC2652ACP TLC2652CP TLC2652AC-14D TLC2652C - 14D — — TLC2652ACN TLC2652CN — — TLC2652Y 70 °C 3 µV TLC2652C-8D — TLC2652CP TLC2652C - 14D — TLC2652CN — –40 °C 1 µV TLC2652AI 8D TLC2652AIP TLC2652AI 14D TLC2652AIN to 1 µV 3 µV TLC2652AI-8D TLC2652A-8D — — TLC2652AIP TLC2652IP TLC2652AI-14D TLC2652I-14D — — TLC2652AIN TLC2652IN — — — 85 °C 3 µV TLC2652A-8D — TLC2652IP TLC2652I-14D — TLC2652IN — –40 °C to 3.5 µV TLC2652Q-8D — — — — — — — 125 °C µ –55 °C to 3 µV TLC2652AM-8D TLC2652AMJG TLC2652AMP TLC2652AM-14D TLC2652AMJ TLC2652AMN TLC2652AMFK to 125 °C µ 3.5 µV TLC2652M-8D TLC2652MJG TLC2652MP TLC2652M-14D TLC2652MJ TLC2652MN TLC2652MFK — The D008 and D014 packages are available taped and reeled. Add R suffix to the device type (e.g., TLC2652AC-8DR). Chips are tested at 25 °C. functional block diagram Clamp Circuit CLAMP OUT C RETURN VDD – Compensation- Biasing Circuit VDD + A B B A IN + IN – CXA CXB External Components Null Main + – + – AB DISTRIBUTION OF TLC2652 INPUT OFFSET VOLTAGE VIO – Input Offset Voltage – µV –3 –2 –1 0 1 2 3 0 4 8 12 16 20 24 28 32 36 150 Units Tested From 1 Wafer Lot VDD ± = ±5 V TA = 25°C N Package CIC 5 4 2 3 6 7 8 Pin numbers shown are for the D (14 pin), JG, and N packages. |
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