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TPIC6C596 데이터시트(PDF) 1 Page - Texas Instruments

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부품명 TPIC6C596
상세설명  POWER LOGIC 8-BIT SHIFT REGISTER
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TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Low rDS(on) ...7 Ω Typ
D Avalanche Energy ...30 mJ
D Eight Power DMOS Transistor Outputs of
100-mA Continuous Current
D 250-mA Current Limit Capability
D ESD Protection . . . 2500 V
D Output Clamp Voltage . . . 33 V
D Enhanced Cascading for Multiple Stages
D All Registers Cleared With Single Input
D Low Power Consumption
description
The TPIC6C596 is a monolithic, medium-voltage,
low-current power 8-bit shift register designed for
use in systems that require relatively moderate
load power such as LEDs. The device contains a
built-in voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other low-current or
medium-voltage loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift
register clock (SRCK) and the register clock
(RCK), respectively. The storage register trans-
fers data to the output buffer when shift register
clear (CLR) is high. When CLR is low, all registers
in the device are cleared. When output enable (G)
is held high, all data in the output buffers is held
low and all drain outputs are off. When G is held
low, data from the storage register is transparent to the output buffers. When data in the output buffers is low,
the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current
capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide
additional hold time for cascaded applications. This will provide improved performance for applications where
clock signals may be skewed, devices are not located near one another, or the system must tolerate
electromagnetic interference.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
logic symbol
2
SRG8
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
8
10
7
15
2
EN3
C2
R
C1
1D
G
RCK
CLR
SRCK
SER IN
3
5
4
11
6
13
12
9
14
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
CLR
G
GND
SRCK
DRAIN7
DRAIN6
DRAIN5
DRAIN4
RCK
SER OUT
D OR N PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
© 2000, Texas Instruments Incorporated


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