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TSB14C01APM 데이터시트(PDF) 8 Page - Texas Instruments |
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TSB14C01APM 데이터시트(HTML) 8 Page - Texas Instruments |
8 / 31 page TSB14C01A, TSB14C01AI, TSB14C01AM 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) device PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IOH = max, VCC = min VCC– 0.8 V VOL Low-level output voltage IOL = min, VCC = max 0.5 V Input current VI = VCC or 0 ±1 µA IOZ Off-state output current VI = VCC or 0 ±10 µA thermal characteristics† PARAMETER TEST CONDITION MIN TYP MAX UNIT R θJA Junction-to-free-air thermal resistance TSB14C01APM, TSB14C01AIPM Board mounted, No air flow 78 °C/W θJA TSB14C01AMHV , 74 °C/W R θJC Junction-to-case thermal resistance TSB14C01APM, TSB14C01AIPM 16 °C/W θJC TSB14C01AMHV 3 °C/W † Thermal characteristics vary depending on die, leadframe, pad size, and mold compound. These values represent typical die and pad sizes for the respective package. The R θJA value decreases as the die pad size increases. Thermal values represent PWB bands with minimal amount of metal. switching characteristics, VCC = 5 V, TA = 25°C (See Note 1) PARAMETER MEASURED TEST CONDITION MIN TYP MAX UNIT tsu D, CTL, LREQ low or high before SCLK high 50% to 50% See Figure 1 7 ns th D, CTL, LREQ low or high after SCLK high 50% to 50% See Figure 1 1 ns td Delay time, SCLK high to D, CTL high or low 50% to 50% See Figure 2 10 ns NOTE 1: These parameters are ensured by design and are not production tested. PARAMETER MEASUREMENT INFORMATION tsu th SCLK D, CTL, LREQ 50% Figure 1. D, CTL, LREQ Input Setup and Hold Timing Waveforms td SCLK D, CTL 50% Figure 2. D, CTL Output Delay Relative to SCLK Timing Waveforms |
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