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UC2827-2 데이터시트(PDF) 4 Page - Texas Instruments |
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UC2827-2 데이터시트(HTML) 4 Page - Texas Instruments |
4 / 15 page www.ti.com (1) f OSC + 0.77 R RT C CT (Hz) (2) t DELAY + R DELAY 200W 10*9 (s) (3) I RT + 2.5 V R RT UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 SLUS365A – APRIL 1999 – REVISED AUGUST 2005 Terminal Functions TERMINAL I/O DESCRIPTION N or NAME Q DW Output of the buck PWM controller. The BUCK output is a floating driver, optimized for controlling the BUCK 2 3 O gate of an N-channel MOSFET. The peak sink and source currents are 1 A. VCC undervoltage faults disables BUCK to an off condition (low). CEA+ 12 13 I Non-inverting input of the current error amplifier. CEA- 13 14 I Inverting input of the current error amplifier Output of the current error amplifier and the inverting input of the PWM comparator of the buck CEAO 6 7 O converter. CSA+ 8 9 I Noninverting input of the current sense amplifier. CSA– 9 10 I Inverting input of the current sense amplifier. Output of the current sense amplifier and the noninverting input of the current limit comparator. When the signal level on this pin exceeds the 3V threshold of the current limit comparator, the buck gate drive CSAO 7 8 O pulse is terminated. This feature is useful to implement cycle-by-cycle current limiting for the buck converter. Provides for the timing capacitor which is connected between CT and GND. The oscillator frequency is set by CT and a resistor RT, connected between pin RT and GND. The CT discharge current is CT 18 20 I approximately 40 x the bias current through the resistor connected to RT. A practical maximum value for the discharge current is 20 mA. The frequency of the oscillator is given by equation(1) A resistor to GND programs the overlap time of the PUSH and PULL outputs of the UC3827-1 and the DELAY 20 22 I dead time of the PUSH and PULL outputs of the UC3827-2. The minimum value of the resistor, RDELAY, is 18 k Ω. The delay or overlap time is given by equation(2) Ground reference for all sensitive setup components not related to driving the outputs. They include all GND 11 12 - timing, voltage sense, current sense, and bypass components. Ground connection for the PUSH and PULL outputs. PGND must be connected to GND at a single point PGND 21 25 - on the printed circuit board. This is imperative to prevent large, high frequency switching currents flowing through the ground metalization inside the device. Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving PULL 22 26 O the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle. Any undervoltage faults will disable PULL to an off condition (low). Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving PUSH 24 28 O the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle. Any undervoltage faults disables PUSH to an off condition (low). The RAMP voltage, after a 700 mV internal level shift, is fed to the noninverting input of the buck PWM comparator. A resistor to VIN and a capacitor to GND provide an input voltage feedforward signal for the buck controller in voltage mode control. In peak current mode control, the RAMP pin receives the RAMP 5 6 I current signal of the buck converter. In an average current mode setup, the RAMP pin has a linearly increasing ramp signal. This waveform may be generated either by connecting RAMP directly to CT, or by connecting both a resistor from VCC to RAMP and a capacitor from RAMP to GND. The output of the +5V on board reference. Bypass this pin with a capacitor to GND. The reference is off REF 15 16 O when the chip is in undervoltage lockout mode.o A resistor to GND programs the charge current of the timing capacitor connected to CT. The charge current approximately equals that shown in equation(3). The charge current should be less than 500 µA RT 17 19 I to keep CT's discharge peak current less than 20 mA, which is CT's maximum practical discharge value. The discharge time, which sets the maximum duty cycle, is set internally and is influenced by the charge current. The source connection for the floating buck switch. The voltage on the SRC pin can exceed VCC but SRC 3 4 I must be lower than 90 V–VVCC. Also, during turn-off transients of the buck switch, the voltage at SRC can go to –2V. 4 |
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