2

FN6749.0

August 8, 2008

Block Diagram

X1

X2

OSCILLATOR

FREQUENCY

TIMER

LOGIC

DIVIDER

CALENDAR

8

CONTROL/

REGISTERS

1Hz

TIME

KEEPING

REGISTERS

ALARM REGS

COMPARE

CONTROL

DECODE

LOGIC

ALARM

(EEPROM)

(EEPROM)

SCL

SDA

SERIAL

INTERFACE

DECODER

4k

EEPROM

ARRAY

REGISTERS

STATUS

(SRAM)

SELECT

VDD

VBAT

32.768kHz

(SRAM)

BATTERY

CIRCUITRY

SWITCH

OSC

COMPENSATION

Pin Descriptions

PIN

NUMBER

SYMBOL

DESCRIPTION

TDFN

1

X1

The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz

quartz crystal.

2

X2

The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz

quartz crystal. (See “Application Section” on page 20.)

Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The

function is set via the control register. This output is an open drain configuration.

4

GND

Ground.

5

SDA

Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain

output and may be wire OR’ed with other open drain or open collector outputs.

6

SCL

The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is

always active (not gated).

7

FVBAT

8

VDD

Power Supply.

ISL12024IRTCZ