STK17TA8
128k X 8 AutoStore™ nvSRAM
with Real Time Clock
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 001-52039 Rev. **
Revised March 02, 2009
Features
■ nvSRAM Combined with Integrated Real Time Clock Functions
(RTC, Watchdog Timer, Clock Alarm, Power Monitor)
■ Capacitor or Battery Backup for RTC
■ 25, 45 ns Read Access and Read/Write Cycle Time
■ Unlimited Read/Write Endurance
■ Automatic nonvolatile STORE on Power Loss
■ Nonvolatile STORE Under Hardware or Software Control
■ Automatic RECALL to SRAM on Power Up
■ Unlimited RECALL Cycles
■ 200K STORE Cycles
■ 20-Year nonvolatile Data Retention
■ Single 3 V +20%, -10% Power Supply
■ Commercial and Industrial Temperatures
■ 48-pin 300-mil SSOP Package (RoHS-Compliant)
Description
The Cypress STK17TA8 combines a 1 Mb nonvolatile static RAM
(nvSRAM) with a full featured real time clock in a reliable,
monolithic integrated circuit.
The 1 Mb nvSRAM is a fast static RAM with a nonvolatile
Quantum Trap storage element included with each memory cell.
The SRAM provides the fast access and cycle times, ease of use
and unlimited read and write endurance of a normal SRAM. Data
transfers automatically to the nonvolatile storage cells when
power loss is detected (the STORE operation). On power up,
data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
Alarm function is programmable for one-time alarms or periodic
minutes, hours, or days alarms. There is also a programmable
watchdog timer for processor control.
Logic Block Diagram
COLUMN DEC
G
E
W
COLUMN I/O
POWER
CONTROL
HSB
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
A15 – A0
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
Quantum Trap
1024 X 1024
STATIC RAM
ARRAY
1024 X 1024
STORE
RECALL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0 A1 A2 A3 A4 A10 A11
VCC
VCAP
RTC
MUX
A16 – A0
X1
X2
INT
VRTCbat
VRTCcap
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