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AD7193BRUZ 데이터시트(PDF) 6 Page - Analog Devices

부품명 AD7193BRUZ
상세설명  4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
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AD7193
Rev. A | Page 6 of 56
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments1
SYSTEM CALIBRATION2
Full-Scale Calibration Limit
1.05 × FS
V
Zero-Scale Calibration
Limit
−1.05 × FS
V
Input Span
0.8 × FS
2.1 × FS
V
POWER REQUIREMENTS7
Power Supply Voltage
AVDD − AGND
3
5.25
V
DVDD − DGND
2.7
5.25
V
Power Supply Currents
AIDD Current
0.85
1
mA
Gain = 1, buffer off
1
1.25
mA
Gain = 1, buffer on
2.8
3.6
mA
Gain = 8, buffer off
3.2
3.9
mA
Gain = 8, buffer on
3.8
4.7
mA
Gain = 16 to 128, buffer off
4.3
5.3
mA
Gain = 16 to 128, buffer on
DIDD Current
0.35
0.4
mA
DVDD = 3 V
0.5
0.6
mA
DVDD = 5 V
1.5
mA
External crystal used
IDD
3
μA
Power-down mode
1 Temperature range: −40°C to +105°C.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.
4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-
scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
5 The analog inputs are configured for differential mode.
6 REJ60 is a bit in the mode register. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous
50 Hz/60 Hz rejection.
7 Digital inputs equal to DVDD or DGND.


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