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STM32F103RBH7TR 데이터시트(Datasheet) 64 Page - STMicroelectronics

부품명 STM32F103RBH7TR
상세내용  Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces
PDF  92 Pages
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제조사  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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Electrical characteristics
STM32F103x8, STM32F103xB
64/92
Doc ID 13587 Rev 11
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 9.
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 41.
SPI characteristics(1)
1.
Remapped SPI1 characteristics to be determined.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
18
MHz
Slave mode
18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
30
70
%
tsu(NSS)
(2)
2.
Based on characterization, not tested in production.
NSS setup time
Slave mode
4tPCLK
ns
th(NSS)
(2)
NSS hold time
Slave mode
2tPCLK
tw(SCKH)
(2)
tw(SCKL)
(2) SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
60
tsu(MI)
(2)
tsu(SI)
(2)
Data input setup time
Master mode
5
Slave mode
5
th(MI)
(2)
Data input hold time
Master mode
5
th(SI)
(2)
Slave mode
4
ta(SO)
(2)(3)
3.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access
time
Slave mode, fPCLK = 20 MHz
0
3tPCLK
tdis(SO)
(2)(4)
4.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable
time
Slave mode
2
10
tv(SO)
(2)(1) Data output valid time Slave mode (after enable edge)
25
tv(MO)
(2)(1) Data output valid time Master mode (after enable edge)
5
th(SO)
(2)
Data output hold time
Slave mode (after enable edge)
15
th(MO)
(2)
Master mode (after enable edge)
2




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