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TSC80C51-12IE 데이터시트(PDF) 5 Page - TEMIC Semiconductors |
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TSC80C51-12IE 데이터시트(HTML) 5 Page - TEMIC Semiconductors |
5 / 19 page TSC80C31/80C51 Rev. E (14 Jan.97) 5 MATRA MHS PSEN Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each machine cycle during fetches from external Program Memory. (However, when executing out of external Program Memory, two activations of PSEN are skipped during each access to external Data Memory). PSEN is not activated during fetches from internal Program Memory. PSEN can sink or source 8 LS TTL inputs. It can drive CMOS inputs without an external pullup. EA When EA is held high, the CPU executes out of internal Program Memory (unless the Program Counter exceeds 3 FFFH). When EA is held low, the CPU executes only out of external Program Memory. EA must not be floated. XTAL1 Input to the inverting amplifier that forms the oscillator. Receives the external oscillator signal when an external oscillator is used. XTAL2 Output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used. Idle And Power Down Operation Figure 3. shows the internal Idle and Power Down clock configuration. As illustrated, Power Down operation stops the oscillator. Idle mode operation allows the interrupt, serial port, and timer blocks to continue to function, while the clock to the CPU is gated off. These special modes are activated by software via the Special Function Register, PCON. Its hardware address is 87H. PCON is not bit addressable. Figure 3. Idle and Power Down Hardware. PCON : Power Control Register (MSB) (LSB) SMOD – – – GF1 GF0 PD IDL Symbol Position Name and Function SMOD PCON.7 Double Baud rate bit. When set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2 or 3. – PCON.6 (Reserved) – PCON.5 (Reserved) – PCON.4 (Reserved) GF1 PCON.3 General-purpose flag bit. GF0 PCON.2 General-purpose flag bit. PD PCON.1 Power Down bit. Setting this bit activates power down operation. IDL PCON.0 Idle mode bit. Setting this bit activates idle mode operation. If 1’s are written to PD and IDL at the same time. PD takes, precedence. The reset value of PCON is (000X0000). Idle Mode The instruction that sets PCON.0 is the last instruction executed before the Idle mode is activated. Once in the Idle mode the CPU status is preserved in its entirety : the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM and all other registers maintain their data during idle. Table 1 describes the status of the external pins during Idle mode. There are three ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction to be executed will be the one following the instruction that wrote 1 to PCON.0. |
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