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AD6642EBZ 데이터시트(PDF) 11 Page - Analog Devices

부품명 AD6642EBZ
상세설명  Dual IF Receiver
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
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AD6642
Rev. 0 | Page 11 of 32
Pin No.
Mnemonic
Type
Description
K8
D2+AB
Output
Channel A and Channel B LVDS Output Data 2—True
J8
D2−AB
Output
Channel A and Channel B LVDS Output Data 2—Complement
M8
D3+AB
Output
Channel A and Channel B LVDS Output Data 3—True
L8
D3−AB
Output
Channel A and Channel B LVDS Output Data 3—Complement
K9
D4+AB
Output
Channel A and Channel B LVDS Output Data 4—True
J9
D4−AB
Output
Channel A and Channel B LVDS Output Data 4—Complement
M9
D5+AB
Output
Channel A and Channel B LVDS Output Data 5—True
L9
D5−AB
Output
Channel A and Channel B LVDS Output Data 5—Complement
K10
D6+AB
Output
Channel A and Channel B LVDS Output Data 6—True
J10
D6−AB
Output
Channel A and Channel B LVDS Output Data 6—Complement
M10
D7+AB
Output
Channel A and Channel B LVDS Output Data 7—True
L10
D7−AB
Output
Channel A and Channel B LVDS Output Data 7—Complement
K11
D8+AB
Output
Channel A and Channel B LVDS Output Data 8—True
J11
D8−AB
Output
Channel A and Channel B LVDS Output Data 8—Complement
M11
D9+AB
Output
Channel A and Channel B LVDS Output Data 9—True
L11
D9−AB
Output
Channel A and Channel B LVDS Output Data 9—Complement
K12
D10+AB
Output
Channel A and Channel B LVDS Output Data 10—True
J12
D10−AB
Output
Channel A and Channel B LVDS Output Data 10—Complement
M12
DCO+AB
Output
Data Clock LVDS Output for Channel A and Channel B—True
L12
DCO−AB
Output
Data Clock LVDS Output for Channel A and Channel B—Complement
C9
MODE
Input
Mode Select Pin (Logic Low Enables NSR; Logic High Disables NSR)
C8
SYNC
Input
Digital Synchronization Pin
C7
PDWN
Input
Power-Down Input (Active High)
C6
SCLK
Input
SPI Clock
C5
SDIO
Input/Output
SPI Data
C4
CSB
Input
SPI Chip Select (Active Low)


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