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AD7944BCPZ 데이터시트(PDF) 7 Page - Analog Devices |
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AD7944BCPZ 데이터시트(HTML) 7 Page - Analog Devices |
7 / 28 page AD7944 Rev. 0 | Page 7 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 REF 2 REF 3 REFGND 4 REFGND 5 IN– 13 CNV 14 SDI 15 TURBO 12 SCK 11 DVDD TOP VIEW (Not to Scale) AD7944 NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1, 2 REF AI Reference Output/Input Voltage. When PDREF is low, the internal reference and buffer are enabled, producing 4.096 V on this pin. When PDREF is high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to 5.0 V. Decoupling is required with or without the internal reference and buffer. This pin is referred to the REFGND pins and should be decoupled closely to the REFGND pins with a 10 μF capacitor. 3, 4 REFGND AI Reference Input Analog Ground. 5 IN− AI Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote ground sense. 6 IN+ AI Analog Input. This pin is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to VREF. 7 PDREF DI Internal Reference Power-Down Input. When this pin is low, the internal reference is enabled. When this pin is high, the internal reference is powered down and an external reference must be used. 8 VIO P Input/Output Interface Digital Power. Nominally at the same supply voltage as the host interface (1.8 V, 2.5 V, or 2.7 V). 9 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 10 DGND P Digital Power Ground. 11 DVDD P Digital Power. Nominally at 2.5 V. 12 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 13 CNV DI Convert Input. This input has multiple functions. On its rising edge, it initiates the conversions and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data should be read when CNV is high. 14 SDI DI Serial Data Input. This input has multiple functions. It selects the interface mode of the ADC as follows. Chain mode is selected if SDI is low during the CNV rising edge. In chain mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 14 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In CS mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 15 TURBO DI Conversion Mode Selection. When TURBO is high, the maximum throughput (2.5 MSPS) is achieved, and the ADC does not power down between conversions. When TURBO is low, the maximum throughput is lower (2.0 MSPS), and the ADC powers down between conversions. 16 AVDD P Input Analog Power. Nominally at 2.5 V. 17, 18 AGND P Analog Power Ground. |
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