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930105201 데이터시트(PDF) 6 Page - ATMEL Corporation |
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930105201 데이터시트(HTML) 6 Page - ATMEL Corporation |
6 / 13 page 6 AT60142FT 7726B–AERO–04/09 Data Retention Mode Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention: 1. During data retention chip select CS must be held high within V CC to VCC -0.2V. 2. Output Enable (OE) should be held high to keep the RAM outputs high imped- ance, minimizing power dissipation. 3. During power-up and power-down transitions CS and OE must be kept between VCC + 0.3V and 70% of VCC. 4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages (3V). Figure 1. Data Retention Timing Data Retention Characteristics Parameter Description Min Typ TA = 25°CMax Unit VCCDR VCC for data retention 2.0 – – V tCDR Chip deselect to data retention time 0.0 – – ns tR Operation recovery time tAVAV (1) 1. TAVAV = Read cycle time. –– ns ICCDR (2) 2. CS = VCC, VIN = GND/VCC. Data retention current – 0.700 1.5 (AT60142FT-15) mA 1.3 (AT60142FT-17) |
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