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AD7298BCPZ-RL7 데이터시트(PDF) 8 Page - Analog Devices |
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AD7298BCPZ-RL7 데이터시트(HTML) 8 Page - Analog Devices |
8 / 18 page AD7298 Preliminary Technical Data Rev. PrA | Page 8 of 18 CONTROL REGISTER The control register of the AD7298 is a 16-bit, write-only register. Data is loaded from the DIN pin of the AD7298 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on the DIN line corresponds to the AD7298 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 16 falling clock edges (after the falling edge of CS Table 6. Control Register Bit Functions ) is loaded to the control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 6 and Table 7. On power up the default content of the control register is all zero’s. MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 WRITE REPEAT CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 T SENSE DONTC DONTC EXT_REF T SENSE AVG PD Table 7. Control Register Bit Function Description Bit Mnemonic Description 15 WRITE The value written to this bit of the control register determines whether the following 15 bits are loaded to the control register. If this bit is a 1, the following 15 bits are written to the control register; if it is a 0, then the remaining 15 bits are not loaded to the control register and it remains unchanged. REPEAT This bit enables the repeated conversion of the selected sequence of channels. CH1 to CH8 Channel selection bits: These eight bits are loaded at the end of the current conversion and select which analog input channel is to be converted in the next serial transfer, or they may select the sequence of channels for conversion in the subsequent serial transfers. Each CHX bit corresponds to an analog input channel. A channel or sequence of channels is selected for conversion by writing a 1 to the appropriate CHX bit/bits. Channel address bits corresponding to the conversion result are output on DOUT prior to the 12 bits of data. The next channel to be converted on is selected by the mux on the 14th SCLK falling edge. TSENSE Writing a 1 to this bit enables the temperature conversion. When the temperature sensor is selected for conversion the TSENSE_BUSY pin will go high after the next CS falling edge to indicate that the conversion is in progress, the previous conversion result can be read while the temperature conversion is in progress. Once TSENSE_Busy goes low, CS can be brought low Tx ns later to read the TSENSE conversion result. DONTC Don’t care. EXT_REF Writing a logic 1 to this bit, enables the use of an external reference. The input voltage range for the external reference is 2V to 2.5V. The external reference should not exceed 2.5V or the device performance will be affected. TSENSE AVG Writing a 1 to this bit enables the temperature sensor averaging function. When averaging is enabled, the AD7298 internally computes a running average of the conversion results to determine the final TSENSE result (See page 14 for more details). This mode will reduce the influence of noise on the final TSENSE result. Selecting this feature does not automatically select the TSENSE for conversion. The TSENSE bit must also be set to start a temperature sensor conversion. PD Partial Power Down. This mode is selected by writing a 1 to this bit in the control register. In this mode, some of the internal analog circuitry is powered down. The AD7298 retains the information in the control register while in partial power down mode. The part remains in this mode until a 0 is written to this bit. Table 8. Channel Address bits ADD3 ADD2 ADD1 ADD0 Analog Input Channel 0 0 0 0 VIN1 0 0 0 1 VIN2 0 0 1 0 VIN3 0 0 1 1 VIN4 0 1 0 0 VIN5 0 1 0 1 VIN6 0 1 1 0 VIN7 0 1 1 1 VIN8 1 0 0 0 TSENSE 1 0 0 1 TSENSE with averaging enabled |
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