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ST7522 데이터시트(PDF) 9 Page - Sitronix Technology Co., Ltd. |
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ST7522 데이터시트(HTML) 9 Page - Sitronix Technology Co., Ltd. |
9 / 45 page ST7522 Ver 1.0c 9/45 2002/07/10 The Serial Interface When the serial interface has been selected (P/S = “L”) then when the chip is in active state (CS1 ― = “L” and CS2 = “H”) the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of the eighth serial clock for the processing. The A0 input is used to determine whether or the serial data input is display data or command data; when A0 = “H”, the data is display data, and when A0 = “L” then the data is command data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is a serial interface signal chart. Figure 1 * When the chip is not active, the shift registers and the counter are reset to their initial states. * Reading is not possible while in serial interface mode. * Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation be rechecked on the actual equipment. The Chip Select The ST7522 Series chips have two chip select terminals: CS1 ― and CS2. The MPU interface or the serial interface is enabled only when CS1 ― = “L” and CS2 = “H”. When the chip select is inactive, D0 to D7 enter a high impedance state, and the A0, RD ― , and WR ― inputs are inactive. When the serial interface is selected, the shift register and the counter are reset. CS1 CS2 SI SCL A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 |
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