전자부품 데이터시트 검색엔진 |
|
ST7585 데이터시트(PDF) 8 Page - Sitronix Technology Co., Ltd. |
|
ST7585 데이터시트(HTML) 8 Page - Sitronix Technology Co., Ltd. |
8 / 51 page ST7585 Ver 1.0c 8/51 2009/04/14 Built-in Power System Pins Pin Name Type Description No. of Pins V0O V0I V0S Power LCD driving voltage for commons at negative frame. V0 ≥ VG > VM > VSS ≥ XV0 V0O, V0I & V0S should be separated in ITO layout. V0O, V0I & V0S should be connected together in FPC layout. 2 4 1 XV0O XV0I XV0S Power LCD driving voltage for commons at positive frame. XV0O, XV0I & XV0S should be separated in ITO layout. XV0O, XV0I & XV0S should be connected together in FPC layout. 2 4 1 VGO VGI VGS Power LCD driving voltage for segments. VGO, VGI & VGS should be separated in ITO layout. VGO, VGI & VGS should be connected together in FPC layout. 1.8 ≤ VG < VDD2. 2 4 1 BR I Bias circuit configuration pin for default setting : “L”=1/7; “H”=1/9. This pin sets the default bias ratio after reset. 1 Microprocessor Interface Pins Pin Name Type Description No. of Pins PS[2:0] I Microprocessor interface select pins. PS2 PS1 PS0 Selected Interface “L” “L” “L” 3-Line SPI interface “L” “L” “H” 4-Line SPI interface “L” “H” “L” 6800-series parallel interface “L” “H” “H” 8080-series parallel interface “H” “L” “L” I 2C Interface 3 CSB I Chip select input pin. Interface access is enabled when CSB is “L”. When CSB is non-active (CSB= “H”), D[7:0] pins are high impedance. CSB is not used in serial interfaces and should fix to “H” by VDD1. 1 RESB I Reset input pin. When RESB is “L”, internal initialization is executed. 1 A0 I It determines whether the access is related to data or command. A0= “H” : Indicates that D[7:0] are display data. A0= “L” : Indicates that D[7:0] are control data. A0 is not used in serial interfaces and should fix to “H” by VDD1. 1 RWR I Read/Write execution control pin. When parallel interface is selected: MPU Type RWR Description 6800 series R/W Read/Write control input pin. R/W= “H”: read. R/W= “L”: write. 8080 series /WR Write enable input pin. Signals on D[7:0] will be latched at the rising edge of /WR signal. RWR is not used in serial interfaces and should fix to “H” by VDD1. 1 |
유사한 부품 번호 - ST7585 |
|
유사한 설명 - ST7585 |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |