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ES51966 데이터시트(PDF) 11 Page - Cyrustek corporation |
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ES51966 데이터시트(HTML) 11 Page - Cyrustek corporation |
11 / 25 page 06/04/25 11 ES51966 4 3/4 and 5 3/4 A/D (Peak &Cap) integration (ZI) phase to achieve accurate measurement. In AZ phase, the system offset is stored. The offset error will be eliminated in DINT phase. Thus a higher accuracy could be obtained. In ZI phase, the internal status will be recovered quickly to that of zero input. Thus the succeeding measurements won’t be disturbed by current measurement especially in case of overload. input signal reference voltage Buf Raz Cint integrator output integration time input signal > 0 Fixed integration time Variable deintegration time integration time input signal < 0 Fixed integration time Variable deintegration time fixed slope fixed slope different input different input Figure 2.1 the structure of dual-slope integrator and its output waveform. As mentioned above, the measurement cycle of ES51966 contains four phases: (1) auto zero phase (AZ) (2) input signal integration phase (INT) (3) reference voltage integration phase (DINT) (4) zero integration phase (ZI) Normally, the time ratios of these four phases, AZ, INT, DINT and ZI to the entire measurement cycle are 20%, 20%, 44% and 16% respectively. However the actual duration of each phase depends on conversion rate. The time of each conversion rate are shown in the table below in which voltage/current (without PEAK HOLD or frequency), and diode measurement use this conversion time. C[0:1] CR (times/sec) ZI (ms) AZ (ms) INT (ms) DINT (ms) 01 00 10 11 20 10 5 2 8 16 32 80 10 20 40 100 10 20 40 100 22 44 88 220 Note: Vref = -200 mV. |
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