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AD6659 데이터시트(PDF) 8 Page - Analog Devices

부품명 AD6659
상세설명  Dual IF Receiver
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AD6659
Rev.
| Page 8 of
40
tPD
tSKEW
tCH
tDCO
tCLK
CH A
N – 9
CH B
N – 9
CH A
N – 8
CH B
N – 8
CH A
N – 7
CH B
N – 7
CH A
N – 6
CH B
N – 6
CH A
N – 5
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
tA
Figure 3. CMOS Interleaved Output Timing
TIMING SPECIFICATIONS
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SYNC TIMING REQUIREMENTS
tSSYNC
SYNC to rising edge of CLK setup time (see Figure 4)
0.24
ns
tHSYNC
SYNC to rising edge of CLK hold time (see Figure 4)
0.40
ns
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK (see Figure 50)
2
ns
tDH
Hold time between the data and the rising edge of SCLK (see Figure 50)
2
ns
tCLK
Period of the SCLK (see Figure 50)
40
ns
tS
Setup time between CSB and SCLK (see Figure 50)
2
ns
tH
Hold time between CSB and SCLK (see Figure 50)
2
ns
tHIGH
SCLK pulse width high (see Figure 50)
10
ns
tLOW
SCLK pulse width low (see Figure 50)
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to an output relative
to the SCLK falling edge
10
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an input relative
to the SCLK rising edge
10
ns
Timing Diagram
SYNC
CLK+
tHSYNC
tSSYNC
Figure 4. SYNC Input Timing Requirements


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