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ADRF6655 데이터시트(PDF) 1 Page - Analog Devices

부품명 ADRF6655
상세설명  Broadband Up/Downconverting Mixer with Integrated Fractional-N PLL and VCO
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Broadband Up/Downconverting Mixer with
Integrated Fractional-N PLL and VCO
ADRF6655
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
FEATURES
Broadband active mixer with integrated fractional-N PLL
RF input frequency range: 100 MHz to 2500 MHz
Internal LO frequency range: 1050 MHz to 2300 MHz
Flexible IF output interface
Input P1dB: 12 dBm
Input IP3: 29 dBm
Noise figure (SSB): 12 dB
Voltage conversion gain: 6 dB
Matched 200 Ω output impedance
SPI serial interface for PLL programming
40-lead 6 mm × 6 mm LFCSP
GENERAL DESCRIPTION
The ADRF6655 is a high dynamic range active mixer with
integrated PLL and VCO. The synthesizer uses a programmable
integer-N/fractional-N PLL to generate a local oscillator input
to the mixer. The PLL reference input is nominally 20 MHz. The
reference input can be divided by or multiplied by and then
applied to the PLL phase detector. The PLL can support input
reference frequencies from 10 MHz to 160 MHz. The phase
detector output controls a charge pump whose output is integrated
in an off-chip loop filter. The loop filter output is then applied to an
integrated VCO. The VCO output at 2 × fLO is then applied to a local
oscillator (LO) divider as well as to a programmable PLL divider.
The programmable divider is controlled by an Σ-Δ modulator
(SDM). The modulus of the SDM can be programmed between
1 and 2047.
The broadband, active mixer employs a bias adjustment to allow
for enhanced IP3 performance at the expense of increased supply
current. The mixer provides an input IP3 exceeding 25 dBm
with 12 dB single sideband NF under typical conditions. The IIP3
can be boosted to ~29 dBm with roughly 20 mA of additional
supplied current. The mixer provides a typical voltage conversion
gain of 6 dB with a 200 Ω differential IF output impedance. The
IF output can be externally matched to support upconversion over
a limited frequency range.
The ADRF6655 is fabricated using an advanced silicon-germanium
BiCMOS process. It is packaged in a 40-lead, exposed-paddle,
Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a
−40°C to +85°C temperature range.
FUNCTIONAL BLOCK DIAGRAM
MUX
RSET
NC
LOSEL
LON
LOP
MUX
LOSEL
TEMP
SENSOR
GND
IP3SET
GND
VCCLO
BUFFER
BUFFER
OUTP
VCCLO
+
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
PRESCALER
3.3V LDO
VCO LDO
2.5V LDO
LE
CLK
SPI
INTERFACE
DATA
MUXOUT
REFIN
ADRF6655
34
GND
GND
35
19
OUTN
18
17
16
DECL3
40
VTUNE
39
DECL2 VCC2
9
10
5
DECL1
2
VCC1
1
8
6
GND 7
14
GND 15
13
12
38
GND 11
37
36
GND
31
NC
NC
32
33
28
VCCMIX
27
INP
26
INN
25
GND
24
GND
23
VCCV2I
22
GND
GND
21
20
29
30
PHASE
FREQUENCY
DETECTOR
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
REG
MODULUS
INTEGER
REG
N COUNTER
21 TO 123
GND
4
CP
3
×2
÷2
÷4
DIVIDER
÷2 OR ÷3
VCO
CORE
Figure 1.


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