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BU3073HFV-TR 데이터시트(PDF) 3 Page - Rohm |
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BU3073HFV-TR 데이터시트(HTML) 3 Page - Rohm |
3 / 21 page 3/20 BU3073HFV(Ta=25℃, VDD=3.3V, Crystal frequency=48.0000MHz, unless otherwise specified.) Parameter Symbol Min. Typ. Max. Unit Conditions Output H voltage VOH 2.8 - - V IOH=-4.0mA Output L voltage VOL - - 0.5 V IOL=4.0mA Consumption current 1 IDD1 - 11 16 mA PD=H, at no load Consumption current 2 IDD2 - - 5 mA PD=L Output frequency CLK_375 - 24.3750 - MHz SEL=L, IN*65/16/8 CLK_545 - 24.5454 - MHz SEL=H, IN*45/11/8 The following parameters represent design guaranteed performance. Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD Period-Jitter 1σ PJsSD - 45 - psec ※ 1 Long-Term-Jitter MIN-MAX LTJsABS - 0.9 1.5 nsec MIN-MAX of long-term jitter (100 sec from trigger) Rise time tr - 2.5 - nsec Period of transition time required for the output to reach 80% from 20% of VDD. Provided with 15pF output load. Fall time tf - 2.5 - nsec Period of transition time required for the output to reach 20% from 80% of VDD. Provided with 15pF output load. Output Lock time tLOCK - - 1 msec ※ 3 Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN. If the input frequency is set to 48.0000MHz, the output frequency will be as listed above. BU3076HFV(Ta=25℃, VDD=3.3V, Crystal frequency=27.0000MHz, unless otherwise specified.) Parameter Symbol Min. Typ. Max. Unit Conditions Output H voltage VOH 2.8 - - V IOH=-4.0mA Output L voltage VOL - - 0.5 V IOL=4.0mA Pull-down resistance Rpd 25 50 100 KΩ Pull-down resistance on input pin Consumption current 1 IDD1 - 10 15 mA 54MHz output, at no load Consumption current 2 IDD2 - 12 18 mA 67.5MHz output, at no load Standby current IDDst - - 1 μ A OE=L Output frequency CLK_54 - 54.0000 - MHz SEL=L, IN*48/6/4 CLK_67.5 - 67.5000 - MHz SEL=H, IN*60/6/4 The following parameters represent design guaranteed performance. Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD Period-Jitter 1σ PJsSD - 50 - psec ※ 1 Period-Jitter MIN-MAX PJsABS - 300 - psec ※ 2 Rise time tr - 1.5 - nsec Period of transition time required for the output to reach 80% from 20% of VDD. Provided with 15pF output load. Fall time tf - 1.5 - nsec Period of transition time required for the output to reach 20% from 80% of VDD. Provided with 15pF output load. Output Lock time tLOCK - - 200 usec ※ 3 Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN. If the input frequency is set to 27.0000MHz, the output frequency will be as listed above. |
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