전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

74AUP2G79 데이터시트(PDF) 1 Page - NXP Semiconductors

부품명 74AUP2G79
상세설명  Low-power dual D-type flip-flop; positive-edge trigger
Download  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

74AUP2G79 데이터시트(HTML) 1 Page - NXP Semiconductors

  74AUP2G79 Datasheet HTML 1Page - NXP Semiconductors 74AUP2G79 Datasheet HTML 2Page - NXP Semiconductors 74AUP2G79 Datasheet HTML 3Page - NXP Semiconductors 74AUP2G79 Datasheet HTML 4Page - NXP Semiconductors 74AUP2G79 Datasheet HTML 5Page - NXP Semiconductors 74AUP2G79 Datasheet HTML 6Page - NXP Semiconductors 74AUP2G79 Datasheet HTML 7Page - NXP Semiconductors 74AUP2G79 Datasheet HTML 8Page - NXP Semiconductors 74AUP2G79 Datasheet HTML 9Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 21 page
background image
1.
General description
The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on
the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the
clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2.
Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101-C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °Cto+85 °C and −40 °C to +125 °C
74AUP2G79
Low-power dual D-type flip-flop; positive-edge trigger
Rev. 04 — 30 June 2009
Product data sheet


유사한 부품 번호 - 74AUP2G79

제조업체부품명데이터시트상세설명
logo
Nexperia B.V. All right...
74AUP2G79 NEXPERIA-74AUP2G79 Datasheet
279Kb / 19P
   Low-power dual D-type flip-flop; positive-edge trigger
Rev. 11 - 3 December 2020
74AUP2G79-Q100 NEXPERIA-74AUP2G79-Q100 Datasheet
235Kb / 15P
   Low-power dual D-type flip-flop; positive-edge trigger
74AUP2G79DC NEXPERIA-74AUP2G79DC Datasheet
279Kb / 19P
   Low-power dual D-type flip-flop; positive-edge trigger
Rev. 11 - 3 December 2020
74AUP2G79DC-Q100 NEXPERIA-74AUP2G79DC-Q100 Datasheet
235Kb / 15P
   Low-power dual D-type flip-flop; positive-edge trigger
74AUP2G79GN NEXPERIA-74AUP2G79GN Datasheet
279Kb / 19P
   Low-power dual D-type flip-flop; positive-edge trigger
Rev. 11 - 3 December 2020
More results

유사한 설명 - 74AUP2G79

제조업체부품명데이터시트상세설명
logo
NXP Semiconductors
74AUP2G80 NXP-74AUP2G80 Datasheet
95Kb / 18P
   Low-power dual D-type flip-flop; positive-edge trigger
Rev. 02-1 August 2007
logo
Nexperia B.V. All right...
74AUP2G79-Q100 NEXPERIA-74AUP2G79-Q100 Datasheet
235Kb / 15P
   Low-power dual D-type flip-flop; positive-edge trigger
logo
NXP Semiconductors
74AUP2G80 PHILIPS-74AUP2G80 Datasheet
94Kb / 18P
   Low-power dual D-type flip-flop; positive-edge trigger
Rev. 01-25 August 2006
74AUP2G80 NXP-74AUP2G80_08 Datasheet
111Kb / 20P
   Low-power dual D-type flip-flop; positive-edge trigger
Rev. 04-2 June 2008
logo
Nexperia B.V. All right...
74AUP2G79 NEXPERIA-74AUP2G79 Datasheet
279Kb / 19P
   Low-power dual D-type flip-flop; positive-edge trigger
Rev. 11 - 3 December 2020
74AUP2G80 NEXPERIA-74AUP2G80 Datasheet
279Kb / 19P
   Low-power dual D-type flip-flop; positive-edge trigger
Rev. 11 - 7 December 2020
logo
NXP Semiconductors
74AUP1G79 PHILIPS-74AUP1G79 Datasheet
97Kb / 20P
   Low-power D-type flip-flop; positive-edge trigger
Rev. 01-12 September 2005
74AUP1G79 NXP-74AUP1G79 Datasheet
113Kb / 20P
   Low-power D-type flip-flop; positive-edge trigger
Rev. 03-3 August 2009
74AUP1G80 NXP-74AUP1G80 Datasheet
103Kb / 18P
   Low-power D-type flip-flop; positive-edge trigger
Rev. 01-20 October 2006
logo
Nexperia B.V. All right...
74AUP1G79 NEXPERIA-74AUP1G79 Datasheet
305Kb / 21P
   Low-power D-type flip-flop; positive-edge trigger
Rev. 8 - 24 January 2022
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com