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74HCT259N 데이터시트(PDF) 9 Page - NXP Semiconductors

부품명 74HCT259N
상세설명  8-bit addressable latch
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제조업체  NXP [NXP Semiconductors]
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74HC_HCT259_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 February 2009
9 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
tsu
set-up time
D, An to LE; see Figure 10
and Figure 11
VCC = 2.0 V
80
19
-
100
-
120
-
ns
VCC = 4.5 V
16
7
-
20
-
24
-
ns
VCC = 6.0 V
14
6
-
17
-
20
-
ns
th
hold time
D to LE; see Figure 10
and Figure 11
VCC = 2.0 V
0
−19
-
0
-
0
-
ns
VCC = 4.5 V
0
−6-
0
-
0
-
ns
VCC = 6.0 V
0
−5-
0
-
0
-
ns
An to LE; see Figure 10
and Figure 11
VCC = 2.0 V
2
−11
-
2
-
2
-
ns
VCC = 4.5 V
2
−4-
2
-
2
-
ns
VCC = 6.0 V
2
−3-
2
-
2
-
ns
CPD
power
dissipation
capacitance
fi = 1 MHz;
VI = GND to VCC
[4]
-19
-
-
-
-
-
pF
74HCT259
tpd
propagation
delay
D to Qn; see Figure 6
[2]
VCC = 4.5 V
-
23
39
-
49
-
59
ns
VCC = 5.0 V; CL =15pF
-
20
-
-
-
-
-
ns
An to Qn; see Figure 7
[2]
VCC = 4.5 V
-
25
41
51
62
ns
VCC = 5.0 V; CL =15pF
-
20
-
-
-
-
-
ns
LE to Qn; see Figure 8
[2]
VCC = 4.5 V
-
22
38
-
48
-
57
ns
VCC = 5.0 V; CL =15pF
-
20
-
-
-
-
-
ns
tPHL
HIGH to LOW
propagation
delay
MR to Qn; see Figure 9
VCC = 4.5 V
-
23
39
-
49
-
59
ns
VCC = 5.0 V; CL =15pF
-
20
-
-
-
-
-
ns
tt
transition time
see Figure 8
[3]
VCC = 4.5 V
-
7
15
-
19
-
22
ns
tW
pulse width
LE HIGH or LOW;
see Figure 8
VCC = 4.5 V
19
11
-
24
-
29
-
ns
MR LOW; see Figure 9
VCC = 4.5 V
18
10
-
23
-
27
-
ns
tsu
set-up time
D, An to LE; see Figure 10
and Figure 11
VCC = 4.5 V
17
10
-
21
-
26
-
ns
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter
Conditions
25
°C
−40 °Cto+85 °C −40 °C to +125 °C Unit
Min
Typ[1] Max
Min
Max
Min
Max


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