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74LVC1G14GF 데이터시트(PDF) 9 Page - NXP Semiconductors |
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74LVC1G14GF 데이터시트(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 9 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 15. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula: Padd =fi × (tr ×∆ICC(AV) +tf ×∆ICC(AV)) × VCC where: Padd = additional power dissipation (µW); fi = input frequency (MHz); tr = input rise time (ns); 10 % to 90 %; tf = input fall time (ns); 90 % to 10 %; ∆I CC(AV) = average additional supply current (µA). Average ∆I CC(AV) differs with positive or negative input transitions, as shown in Figure 12. An example of a relaxation circuit using the 74LVC1G14 is shown in Figure 13. Linear change of VI between 0.8 V to 2.0 V. All values given are typical unless otherwise specified. Fig 12. Average additional supply current as a function of supply voltage 02 6 12 0 8 6 4 2 10 mna642 4 VCC (V) average ICC (mA) negative-going edge positive-going edge Fig 13. Relaxation oscillator mna035 R C f 1 T --- 1 0.5 RC × ---------------------- ≈ = |
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