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ADC0804S050 데이터시트(PDF) 10 Page - NXP Semiconductors |
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10 / 19 page ADC0804S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 14 August 2008 10 of 19 NXP Semiconductors ADC0804S030/040/050 Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz [7] Effective bits are obtained via a Fast Fourier transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to SIgnal-to-Noise-And-Distortion (SINAD) ratio: SINAD = ENOB × 6.02 + 1.76 dB. [8] Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. [9] Measurement carried out using video analyzer VM700A, where the video analog signal is reconstructed through a digital-to-analog converter. [10] Output data acquisition: the output data is available after the maximum delay time of td(0). For 50 MHz version NXP recommend the lowest possible output load. 11. Additional information relating to Table 6 Fig 3. Explanation of Table 6 Table note 3 014aaa555 RT RB RM Rlad ROT RL RL RL RL IL ROB code 255 code 0 Table 7. Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V, VRT = 3.67 V) Code Vi(a)(p-p) (V) IR Binary outputs D7 to D0 Two’s complement outputs D7 to D0 Underflow < 1.475 0 0000 0000 10 0000 00 0 1.475 1 0000 0000 10 0000 00 1 - 1 0000 0001 10 0000 01 ↓ - ↓↓ ↓ 254 - 1 1111 1110 01 1111 10 255 3.495 1 1111 1111 01 1111 11 Overflow > 3.495 0 1111 1111 01 1111 11 |
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