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7 / 36 page ADC1010S_SER_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 — 9 April 2010 7 of 36 NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs [1] Typical values measured at VDDA =3V, VDDO =1.8 V, Tamb =25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA =3V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Digital outputs, CMOS mode: pins D9 to D0, OTR, DAV Output levels, VDDO = 3 V VOL LOW-level output voltage IOL = <tbd> OGND - 0.2VDDO V VOH HIGH-level output voltage IOH = <tbd> 0.8VDDO -VDDO V IOL LOW-level output current 3-state; output level = 0 V - <tbd> - μA IOH HIGH-level output current 3-state; output level = VDDA - <tbd> - μA CO output capacitance high impedance; OE =HIGH - 3 - pF Output levels, VDDO = 1.8 V VOL LOW-level output voltage IOL = <tbd> OGND - 0.2VDDO V VOH HIGH-level output voltage IOH = <tbd> 0.8VDDO -VDDO V Digital outputs, LVDS mode: pins D9P to D0P, D9M to D0M, DAVP and DAVM Output levels, VDDO = 3 V only, RL = 100 Ω VO(offset) output offset voltage output buffer current set to 3.5 mA -1.2 - V VO(dif) differential output voltage output buffer current set to 3.5 mA -350 - mV CO output capacitance - <tbd> - pF Analog inputs: pins INP and INM II input current −5- +5 μA RI input resistance - <tbd> - Ω CI input capacitance - 5 - pF VI(cm) common-mode input voltage VINP =VINM 0.9 1.5 2 V Bi input bandwidth - 600 - MHz VI(dif) differential input voltage peak-to-peak 1 2 V Common mode output voltage: pin VCM VO(cm) common-mode output voltage - VDDA /2 - V IO(cm) common-mode output current - <tbd> - μA I/O reference voltage: pin VREF VVREF voltage on pin VREF output 0.5 - 1 V input 0.5 - 1 V Accuracy INL integral non-linearity −0.4 ±0.07 +0.4 LSB DNL differential non-linearity guaranteed no missing codes −0.06 ±0.04 +0.06 LSB Eoffset offset error - ±2- mV EG gain error full-scale ±0.5 % Supply PSRR power supply rejection ratio 100 mV (p-p) on VDDA -35 - dBc Table 6. Static characteristics[1] …continued Symbol Parameter Conditions Min Typ Max Unit |
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