CS4226

DS188F4

9

Notes: 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL

Notes: 15. CLKOUT Jitter is for 256×FS selected as output frequency measured from falling edge to falling edge.

Jitter is greater for 384×Fs and 512×Fs as selected output frequency.

16. For CLKOUT frequency equal to 1×Fs, 384×Fs, and 512×Fs. See Master Clock Output section.

DIGITAL CHARACTERISTICS

Parameter

Symbol

Min

Max

Units

SCL Clock Frequency

-

100

kHz

Bus Free Time Between Transmissions

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

4.0

µs

Clock Low Time

4.7

µs

Clock High Time

4.0

µs

Setup Time for Repeated Start Condition

4.7

µs

SDA Hold Time from SCL Falling

(Note 14)

0

µs

SDA Setup Time to SCL Rising

250

ns

Rise Time of Both SDA and SCL Lines

1

µs

Fall Time of Both SDA and SCL Lines

300

ns

Setup Time for Stop Condition

4.7

µs

Parameter

Symbol

Min

Typ

Max

Units

Input Resistance

-10

-

k

Ω

Input Voltage

200

-

-

mVpp

Input Hysteresis

-50

-

mV

Input Sample Frequency

30

-

50

kHz

CLKOUT Jitter

(Note 15)

-

200

-

ps RMS

CLKOUT Duty Cycle (high time/cycle time)

(Note 16)

40

50

60

%

Parameter

Symbol

Min

Typ

Max

Units

High-level Input Voltage

(except RX1)

2.8

-

(VD+)+0.3

V

Low-level Input Voltage

(except RX1)

-0.3

-

0.8

V

(VD+)-1.0

-

-

V

--

0.4

V

Input Leakage Current

(Digital Inputs)

-

-

10

µA

Output Leakage Current

(High-Impedance Digital Outputs)

-

-

10

µA