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CDCE72010 데이터시트(PDF) 10 Page - Texas Instruments |
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CDCE72010 데이터시트(HTML) 10 Page - Texas Instruments |
10 / 73 page AC/DC CHARACTERISTICS (CONTINUED) CDCE72010 SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com over the specified industrial temperature range of –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT LVDS Output fclk Output frequency Open loop config. load, See Figure 2 0 800 MHz |VOD| Differential output voltage RL = 100 Ω 160 270 mV LVDS VOD magnitude ΔVOD 50 mV change VOS Offset voltage –40°C to 85°C 1.24 V ΔVOS VOS magnitude change 40 mV Short circuit VOUT+ to VOUT = 0 27 mA ground Short circuit VOUT– to VOUT = 0 27 mA ground Reference to output VCXO at 491.52MHz, Output 1 is divide by phase offset without using 16 and reference at 30.72MHz, M and N tpho (2) 14 ns available delay delays are fixed to one value (set to 0), PFD: adjustment 240kHz, (M and N = 128) tpd(LH)/ Propagation delay time, Crosspoint to crosspoint, load, see Figure 2 3.0 ns tpd(HL) VCXO_IN to output Divide by 1 for all dividers 45 Skew, output to output Divide by 16 for all dividers 50 tsk(o)(3) ps LVDS output Divide by 1 for divider 1 2800 Divide by 16 for all other dividers Output capacitance on Y0 CO VCC = 3.3 V; VO = 0 V or VCC 5 pF to Y8 CO Output capacitance on Y9 VCC = 3.3 V; VO = 0 V or VCC 5 7 pF Power-down output IOPDH VO = VCC 25 µA current Power-down output IOPDL VO = 0V 5 µA current Duty cycle 45 55 % tr/tf Rise and fall time 20% to 80% of Voutpp 110 140 160 ps LVCMOS-TO-LVDS(4) Output skew between tskP_C LVCMOS and LVDS Crosspoint to VCC/2 0.9 1.4 1.9 ns outputs (1) All typical values are at VCC = 3.3 V, TA = 25°C. (2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and VCXO delay N). (3) The tsk(o) specification is only valid for equal loading of all outputs. (4) Operating the LVCMOS or LVDS outputs above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS. 10 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): CDCE72010 |
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