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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LM3S8630-EQC25-A2T 데이터시트(PDF) 44 Page - Texas Instruments |
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LM3S8630-EQC25-A2T 데이터시트(HTML) 44 Page - Texas Instruments |
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44 / 546 page  If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect to a reference clock. The reference clock can be the core clock or an external clock source. SysTick Control and Status Register Use the SysTick Control and Status Register to enable the SysTick features. The reset is 0x0000.0000. Description Reset Type Name Bit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 31:17 Count Flag Returns 1 if timer counted to 0 since last time this was read. Clears on read by application. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read. 0 R/W COUNTFLAG 16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 15:3 Clock Source Description Value External reference clock. (Not implemented for Stellaris microcontrollers.) 0 Core clock 1 If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are unpredictable. 0 R/W CLKSOURCE 2 Tick Interrupt Description Value Counting down to 0 does not generate the interrupt request to the NVIC. Software can use the COUNTFLAG to determine if ever counted to 0. 0 Counting down to 0 pends the SysTick handler. 1 0 R/W TICKINT 1 Enable Description Value Counter disabled. 0 Counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting. 1 0 R/W ENABLE 0 SysTick Reload Value Register Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. April 04, 2010 44 Texas Instruments-Production Data ARM Cortex-M3 Processor Core |
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