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LM3S8630-EQC50-A2T 데이터시트(PDF) 27 Page - Texas Instruments |
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LM3S8630-EQC50-A2T 데이터시트(HTML) 27 Page - Texas Instruments |
27 / 546 page – 1.25 DMIPS/MHz ■ JTAG – IEEE 1149.1-1990 compatible Test Access Port (TAP) controller – Four-bit Instruction Register (IR) chain for storing JTAG instructions – IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST – ARM additional instructions: APACC, DPACC and ABORT – Integrated ARM Serial Wire Debug (SWD) ■ Hibernation – System power control using discrete external regulator – Dedicated pin for waking from an external signal – Low-battery detection, signaling, and interrupt generation – 32-bit real-time counter (RTC) – Two 32-bit RTC match registers for timed wake-up and interrupt generation – Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal – RTC predivider trim for making fine adjustments to the clock rate – 64 32-bit words of non-volatile memory – Programmable interrupts for RTC match, external wake, and low battery events ■ Internal Memory – 128 KB single-cycle flash • User-managed flash block protection on a 2-KB block basis • User-managed flash data programming • User-defined and managed flash-protection block – 32 KB single-cycle SRAM ■ GPIOs – 10-31 GPIOs, depending on configuration – 5-V-tolerant input/outputs – Programmable control for GPIO interrupts • Interrupt generation masking • Edge-triggered on rising, falling, or both 27 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S8630 Microcontroller |
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