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DLPC200 데이터시트(PDF) 4 Page - Texas Instruments |
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DLPC200 데이터시트(HTML) 4 Page - Texas Instruments |
4 / 41 page DLPC200 DLPS014A – APRIL 2010 – REVISED MAY 2010 www.ti.com PROJECTOR IMAGE AND CONTROL PORT SIGNALS The DLPC200 provides two input ports for graphics and motion video inputs. The signals listed below support the two input interface modes. Below are the two input image interface modes, signal descriptions, and pins needed on the DLPC200. • PORT 1, 28 pins (HDMI connector) – PORT1_D(23-0) – Projector Data – PORT1_VSYNC – Vertical Sync – PORT1_HSYNC – Horizontal Sync – PORT1_IVALID – Data Enable – PORT1_CLK – Projector Clock (rising edge, or falling edge, to capture input data) • PORT 2, 28 pins (Expansion connector) – PORT2_D(23-0) – Projector Data – PORT2_VSYNC – Vertical Sync – PORT2_HSYNC – Horizontal Sync – PORT2_IVALID – Data Enable – PORT2_CLK – Projector Clock (rising edge, or falling edge, to capture input data) Two control interfaces, USB and SPI, are provided to configure the DLPC200, as well as to transmit pattern data to memory for structured light mode. Below are the pins needed for the SPI and USB control interfaces. • USB, 48 MHz – USB_CLK - USB clock – USB_CTRL1 - FIFO full flag – USB_CTRL2 - FIFO empty flag – USB_FD(15-0) - USB data – USB_PA02 - FIFO output enable for reads – USB_PA04 - FIFO address bit – USB_PA05 - FIFO address bit – USB_RDY1 - Write enable – USB_RDY0 - Read enable • SPI, 5 MHz – SLAVE_SPI_CLK - SPI clock – SLAVE_SPI_ACK - busy signal that holds off additional transactions until the slave has completed processing data – SLAVE_SPI_MISO - output from slave – SLAVE_SPI_MOSI - output from master – SLAVE_SPI_CS - Slave select Images are displayed via control of the DMD and DAD. The DLPC200 DMD interface consists of a 200 MHz (nominal) half bus DDR output-only interface with LVDS signaling. The serial communications port (SCP), 125 kHz nominal, is used to read or write control data to both the DMD and the DAD. The signals listed below support data transfer to the DMD and DAD. • DMD, 200 MHz – DMD_CLK_AP, DMD_CLK_AN - DMD clock for A – DMD_CLK_BP, DMD_CLK_BN - DMD clock for B – DMD_DAT_AP, DMD_DAT_AN(1,3,5,7,9,11,13,15) - Data bus A (odd numbered pins are used for half bus) – DMD_DAT_BP, DMD_DAT_BN(1,3,5,7,9,11,13,15) - Data bus B (odd numbered pins are used for half bus) – DMD_SCRTL_AP, DMD_SCRTL_AN - S-control for A – DMD_SCRTL_BP, DMD_SCRTL_BN - S-control for B 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPC200 |
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