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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DAC5682ZIRGCR 데이터시트(PDF) 11 Page - Texas Instruments |
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DAC5682ZIRGCR 데이터시트(HTML) 11 Page - Texas Instruments |
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11 / 59 page  DAC5682Z www.ti.com ........................................................................................................................................................ SLLS853C – AUGUST 2007 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Data output delay after td(Data) 10 ns falling edge of SCLK Minimum RESETB pulse tRESET 25 ns width CLOCK INPUT (CLKIN/CLKINC) Duty cycle 50% Differential voltage(3) 0.4 1 V CLKIN/CLKINC input CLKVDD V common mode ÷2 PHASE LOCKED LOOP DAC output at 600 kHz offset, 100 MHz, 0-dBFS tone, 2X4, fDATA = 250 MSPS, CLKIN/C = 250 MHz, –125 PLL_m = '00111', PLL_n = '001', VCO_div2 = 0, PLL_range = '1111', PLL_gain = '00' Phase noise dBc/ Hz DAC output at 6 MHz offset, 100 MHz, 0-dBFS tone, 2X4, fDATA = 250 MSPS, CLKIN/C = 250 MHz, –146 PLL_m = '00111', PLL_n = '001', VCO_div2 = 0, PLL_range = '1111', PLL_gain = '00' PLL_gain = '00', PLL_range = '0000' (0) 160 290 MHz 220 MHz/V PLL_gain = '01', PLL_range = '0001' (1) 290 460 MHz 300 MHz/V PLL_gain = '01', PLL_range = '0010' (2) 400 520 MHz 260 MHz/V PLL_gain = '01', PLL_range = '0011' (3) 480 570 MHz 240 MHz/V PLL_gain = '01', PLL_range = '0100' (4) 560 620 MHz 210 MHz/V PLL_gain = '10', PLL_range = '0101' (5) 620 740 MHz 270 MHz/V PLL/VCO Operating PLL_gain = '10', PLL_range = '0110' (6) 690 780 MHz Frequency, 250 MHz/V Typical VCO Gain PLL_gain = '10', PLL_range = '0111' (7) 740 820 MHz 240 MHz/V PLL_gain = '10', PLL_range = '1000' (8) 790 850 MHz 220 MHz/V PLL_gain = '10', PLL_range = '1001' (9) 840 880 MHz 210 MHz/V PLL_gain = '11', PLL_range = '1010' (A) 880 940 MHz 250 MHz/V PLL_gain = '11', PLL_range = '1011' (B) 920 990 MHz 230 MHz/V PLL_gain = '11', PLL_range = '1100' (C) 960 1000 MHz 220 MHz/V PFD Maximum Frequency 160 MHz (3) Driving the clock input with a differential voltage lower than 1V will result in degraded performance. Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): DAC5682Z |
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