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CDCE925PWRG4 데이터시트(PDF) 11 Page - Texas Instruments

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부품명 CDCE925PWRG4
상세설명  PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-V and 3.3-V LVCMOS OUTPUTS
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CDCE925PWRG4 데이터시트(HTML) 11 Page - Texas Instruments

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EEPROM
Xin
Xout
VDD
GND
VDDOUT
Xtal
Y2 = 27 MHz
Y1 = 27 MHz
Y3 = 27 MHz
LV
CMOS
Pdiv1 =1
Y4 = 27 MHz
Y5 = 27 MHz
LV
CMOS
Pdiv5 = 1
Pdiv4 = 1
LV
CMOS
LV
CMOS
Pdiv3 = 1
Pdiv2 = 1
LV
CMOS
Programming
and
SDA/SCL
Register
InputClock
PLL Bypass
PLL 1
PowerDown
PLL Bypass
PLL 2
PowerDown
S0
SDA
SCL
27-MHz
Crystal
ProgrammingBus
“1” = OutputsEnabled
“0” = Outputs 3-State
CDCE925
CDCEL925
www.ti.com
SCAS847F – JULY 2007 – REVISED MARCH 2010
SDA/S1 and SCL/S2 pins of the CDCE925/CDCEL925 are dual-function pins. In default configuration, they are
predefined as SDA/SCL serial programming interface. They can be programmed to control pins (S1/S2) by
setting the relevant bits in the EEPROM. Note that the changes of the bits in the Control Register (bit [6] of byte
02h) have no effect until they are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).
S0 is not a multi use pin; it is a control pin only.
DEFAULT DEVICE SETTING
The internal EEPROM of CDCE925/CDCEL925 is preconfigured as shown in Figure 6 The input frequency is
passed through the output as a default. This allows the device to operate in default mode without the extra
production step of programming it. The default setting appears after power is supplied or after power-down/up
sequence until it is reprogrammed by the user to a different application configuration. A new register setting is
programmed via the serial SDA/SCL interface.
Figure 6. Preconfiguration of CDCE925/CDCEL925 Internal EEPROM
Table 4 shows the factory default setting for the Control Terminal Register (external control pins). Note that even
though eight different register settings are possible, in default configuration, only the first two settings (0 and 1)
can be selected with S0, as S1 and S2 are configured as programming pins in default mode.
Table 4. Factory Default Setting for Control Terminal Register(1)
Y1
PLL1 Settings
PLL2 Settings
Output
Frequency
SSC
Output
Frequency
SSC
Output
External Control Pins
Selection
Selection
Selection
Selection
Selection
Selection
Selection
S2
S1
S0
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
SCL (I2C)
SDA (I2C)
0
3-state
fVCO1_0
off
3-state
fVCO2_0
off
3-state
SCL (I2C)
SDA (I2C)
1
enabled
fVCO1_0
off
enabled
fVCO2_0
off
enabled
(1)
In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any
control-pin function but they are internally interpreted as if S1=0 and S2=0. S0, however, is a control-pin which in the default mode
switches all outputs ON or OFF (as previously predefined).
Copyright © 2007–2010, Texas Instruments Incorporated
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Product Folder Link(s): CDCE925 CDCEL925


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