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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LM3S8730-EQR20-A2T 데이터시트(PDF) 72 Page - Texas Instruments |
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LM3S8730-EQR20-A2T 데이터시트(HTML) 72 Page - Texas Instruments |
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72 / 551 page  Table 6-3. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field (continued) StellarisWare Parameter a Frequency (BYPASS2=1) Frequency (BYPASS2=0) Divisor SYSDIV2 SYSCTL_SYSDIV_64 Clock source frequency/64 3.125 MHz /64 0x3F a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. 6.1.4.3 Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise, the range of supported crystals is 1 to 8.192 MHz. The XTAL bit in the RCC register (see page 85) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. 6.1.4.4 Main PLL Frequency Configuration The main PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency, and enables the main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor. If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 88). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. Table 20-9 on page 512 shows the actual PLL frequency and error for a given crystal choice. The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 85) describes the available crystal choices and default programming of the PLLCFG register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. To configure the external 32-kHz real-time oscillator as the PLL input reference, program the OSCRC2 field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x7. 6.1.4.5 PLL Modes The PLL has two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 85 and page 89). 6.1.4.6 PLL Operation If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 20-8 on page 512). During the relock time, the affected PLL is not usable as a clock reference. June 22, 2010 72 Texas Instruments-Production Data System Control |
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