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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LM3S8730-EQR25-A2T 데이터시트(PDF) 42 Page - Texas Instruments |
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LM3S8730-EQR25-A2T 데이터시트(HTML) 42 Page - Texas Instruments |
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42 / 551 page  2.2.2 Embedded Trace Macrocell (ETM) ETM was not implemented in the Stellaris ® devices. This means Chapters 15 and 16 of the ARM® Cortex™-M3 Technical Reference Manual can be ignored. 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer. The Stellaris ® devices have implemented TPIU as shown in Figure 2-2 on page 42. This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual, however, SWJ-DP only provides SWV output for the TPIU. Figure 2-2. TPIU Block Diagram ATB Interface Asynchronous FIFO APB Interface Trace Out (serializer) Debug ATB Slave Port APB Slave Port Serial Wire Trace Port (SWO) 2.2.4 ROM Table The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical Reference Manual. 2.2.5 Memory Protection Unit (MPU) The Memory Protection Unit (MPU) is included on the LM3S8730 controller and supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 2.2.6 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC): ■ Facilitates low-latency exception and interrupt handling ■ Controls power management ■ Implements system control registers June 22, 2010 42 Texas Instruments-Production Data ARM Cortex-M3 Processor Core |
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