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LM3S8730-EQC25-A2 데이터시트(PDF) 12 Page - Texas Instruments |
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LM3S8730-EQC25-A2 데이터시트(HTML) 12 Page - Texas Instruments |
12 / 551 page List of Registers System Control .............................................................................................................................. 63 Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 77 Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 79 Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 80 Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 81 Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 82 Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 83 Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 84 Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 85 Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 88 Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 89 Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 91 Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 92 Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 94 Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 95 Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 97 Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 99 Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 100 Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 102 Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 104 Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 106 Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 108 Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 110 Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 112 Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 114 Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 116 Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 118 Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 120 Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 121 Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 123 Hibernation Module ..................................................................................................................... 125 Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 133 Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 134 Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 135 Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 136 Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 137 Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 139 Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 140 Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 141 Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 142 Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 143 Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 144 Internal Memory ........................................................................................................................... 145 Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 150 Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 151 June 22, 2010 12 Texas Instruments-Production Data Table of Contents |
유사한 부품 번호 - LM3S8730-EQC25-A2 |
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유사한 설명 - LM3S8730-EQC25-A2 |
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