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LM3S8730-EQR25-A2 데이터시트(PDF) 70 Page - Texas Instruments

부품명 LM3S8730-EQR25-A2
상세설명  Stellaris짰 LM3S8730 Microcontroller
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Figure 6-5. Main Clock Tree
PLL
(400 MHz)
Main OSC
Internal
OSC
(12 MHz)
Internal
OSC
(30 kHz)
÷ 4
Hibernation
Module
(32.768 kHz)
÷ 25
PWRDN
ADC Clock
System Clock
XTALa
PWRDN b
MOSCDIS a
IOSCDIS
a
OSCSRCb,d
BYPASS
b,d
SYSDIV b,d
USESYSDIV a,d
PWMDW a
USEPWMDIV a
PWM Clock
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
÷ 2
÷ 50
CAN Clock
Note:
The figure above shows all features available on all Stellaris® Fury-class devices.
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 6-2 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 6-1 on page 68.
June 22, 2010
70
Texas Instruments-Production Data
System Control


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