전자부품 데이터시트 검색엔진 |
|
SN74AUC1G240YZPR 데이터시트(PDF) 1 Page - Texas Instruments |
|
|
SN74AUC1G240YZPR 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 13 page www.ti.com FEATURES V CC V CC 3 2 4 5 1 OE Y A GND DBVPACKAGE (TOP VIEW) 3 2 4 5 1 OE V CC Y A GND OE GND Y A Seemechanicaldrawingsfordimensions. 1 4 2 3 5 DCKPACKAGE (TOP VIEW) YZP PACKAGE (BOTTOMVIEW) DESCRIPTION/ORDERING INFORMATION SN74AUC1G240 SINGLE BUFFER/DRIVER WITH 3-STATE OUTPUT SCES384I – MARCH 2002 – REVISED FEBRUARY 2007 • Available in the Texas Instruments • Low Power Consumption, 10-µA Max I CC NanoFree™ Package • ±8-mA Output Drive at 1.8 V • Optimized for 1.8-V Operation and Is 3.6-V I/O • Latch-Up Performance Exceeds 100 mA Per Tolerant to Support Mixed-Mode Signal JESD 78, Class II Operation • ESD Protection Exceeds JESD 22 • I off Supports Partial-Power-Down Mode – 2000-V Human-Body Model (A114-A) Operation – 200-V Machine Model (A115-A) • Sub-1-V Operable – 1000-V Charged-Device Model (C101) • Max t pd of 2.5 ns at 1.8 V This bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC1G240 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING(2) NanoFree™ – WCSP (DSBGA) Reel of 3000 SN74AUC1G240YZPR _ _ _UK_ 0.23-mm Large Bump – YZP (Pb-free) –40 °C to 85°C SOT (SOT-23) – DBV Reel of 3000 SN74AUC1G240DBVR U40_ SOT (SC-70) – DCK Reel of 3000 SN74AUC1G240DCKR UK_ (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2002–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
유사한 부품 번호 - SN74AUC1G240YZPR |
|
유사한 설명 - SN74AUC1G240YZPR |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |