AUP

LVC

AUP

AUP

LVC

Static-Power Consumption

(

µA)

Dynamic-Power Consumption

(pF)

3.3-V

3.3-V

0%

20%

40%

60%

80%

100%

0%

20%

40%

60%

80%

100%

−0.5

0

0.5

1

1.5

2

2.5

3

3.5

0

5

10

15

20

25

30

35

40

45

Time − ns

† AUP1G08 data at C

Output

Input

Switching Characteristics

A

Y

2

4

A

Y

1

3

SN74AUP1G07

SCES591F – JULY 2004 – REVISED MAY 2010

www.ti.com

Figure 1. AUP – The Lowest-Power Family

Figure 2. Excellent Signal Integrity

The output of this single buffer/driver is open drain, and can be connected to other open-drain outputs to

implement active-low wired-OR or active-high wired-AND functions.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

preventing damaging current backflow through the device when it is powered down.

ORDERABLE PART

TOP-SIDE

NUMBER

NanoStar – WCSP (DSBGA)

Reel of 3000

SN74AUP1G07YFPR

_ _ _ HV_

0.23-mm large bump – YFP

NanoStar – WCSP (DSBGA)

Reel of 3000

SN74AUP1G07YZPR

_ _ _ HV_

0.23-mm large bump – YZP (Pb-free)

QFN – DRY

Reel of 5000

SN74AUP1G07DRYR

HV

–40°C to 85°C

uQFN – DSF

Reel of 5000

SN74AUP1G07DSFR

HV

SOT (SOT-23) – DBV

Reel of 3000

SN74AUP1G07DBVR

H07_

SOT (SC-70) – DCK

Reel of 3000

SN74AUP1G07DCKR

HV_

SOT (SOT-553) – DRL

Reel of 4000

SN74AUP1G07DRLR

HV_

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3)

DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.

YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

FUNCTION TABLE

INPUT

OUTPUT

A

Y

H

H

L

L

LOGIC DIAGRAM (POSITIVE LOGIC)

(DBV, DCK, DRL, DRY, DRT, and YZP Packages)

(YFP Package)

2

Submit Documentation Feedback

Copyright © 2004–2010, Texas Instruments Incorporated

Product Folder Link(s): SN74AUP1G07