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LM3S8630-EQC50-A2T 데이터시트(PDF) 81 Page - Texas Instruments |
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LM3S8630-EQC50-A2T 데이터시트(HTML) 81 Page - Texas Instruments |
81 / 550 page Register 4: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved BORRIS reserved PLLLRIS reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 31:7 PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts. 0 RO PLLLRIS 6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 5:2 Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition is currently active. This is an unregistered signal from the brown-out detection circuit. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. 0 RO BORRIS 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 0 81 June 22, 2010 Texas Instruments-Production Data Stellaris® LM3S8630 Microcontroller |
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