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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SSTVF16859 데이터시트(PDF) 11 Page - NXP Semiconductors |
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SSTVF16859 데이터시트(HTML) 11 Page - NXP Semiconductors |
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11 / 23 page  9397 750 15157 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 19 July 2005 11 of 23 Philips Semiconductors SSTVF16859 13-bit 1 : 2 SSTL_2 registered buffer for DDR 11. Dynamic characteristics [1] This parameter is not necessarily production tested. [2] Data inputs must be below a minimum time to tACT(max), after RESET is taken HIGH. [3] Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max), after RESET is taken LOW. [4] For data signal input slew rate ≥ 1 V/ns. [5] For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. [6] CK, CK signals input slew rates are ≥ 1 V/ns. [1] This parameter is not necessarily production tested. [2] Data inputs must be below a minimum time to tACT(max), after RESET is taken HIGH. [3] Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max), after RESET is taken LOW. [4] For data signal input slew rate ≥ 1 V/ns. [5] For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. [6] CK, CK signals input slew rates are ≥ 1 V/ns. Table 9: Timing requirements (PC1600-PC2700) At recommended operating conditions; VDD = 2.5 V ± 0.2 V; Tamb =0 °Cto+70 °C; unless otherwise specified. See Figure 11. Symbol Parameter Conditions Min Typ Max Unit fclock clock frequency - - 200 MHz tW pulse duration, CK, CK, HIGH or LOW 2.5 - - ns tACT differential inputs active time [1] [2] --22 ns tINACT differential inputs inactive time [1] [3] --22 ns tsu setup time, fast slew rate data before CK ↑, CK↓ [4] [6] 0.65 - - ns setup time, slow slew rate data before CK ↑, CK↓ [5] [6] 0.75 - - ns th hold time, fast slew rate data after CK ↑, CK↓ [4] [6] 0.75 - - ns hold time, slow slew rate data after CK ↑, CK↓ [5] [6] 0.9 - - ns Table 10: Timing requirements (PC3200) At recommended operating conditions; VDD = 2.6 V ± 0.1 V; Tamb =0 °Cto+70 °C; unless otherwise specified. See Figure 11. Symbol Parameter Conditions Min Typ Max Unit fclock clock frequency - - 210 MHz tW pulse duration, CK, CK, HIGH or LOW 2.5 - - ns tACT differential inputs active time [1] [2] --22 ns tINACT differential inputs inactive time [1] [3] --22 ns tsu setup time, fast slew rate data before CK ↑, CK↓ [4] [6] 0.65 - - ns setup time, slow slew rate data before CK ↑, CK↓ [5] [6] 0.75 - - ns th hold time, fast slew rate data after CK ↑, CK↓ [4] [6] 0.65 - - ns hold time, slow slew rate data after CK ↑, CK↓ [5] [6] 0.8 - - ns |
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