KM432S2030C datasheet(7/43 Pages) SAMSUNG

부품명	KM432S2030C

상세설명	2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

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제조업체	SAMSUNG [Samsung semiconductor]

홈페이지	http://www.samsung.com/Products/Semiconductor

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KM432S2030C

CMOS SDRAM

REV. 1.1 Mar. '99

- 7 -

AC OPERATING TEST CONDITIONS (VDD = 3.3V

± 0.3V, TA = 0 to 70°C)

Parameter

Value

Unit

AC input levels (Vih/Vil)

2.4/0.4

V

Input timing measurement reference level

1.4

V

Input rise and fall time

tr/tf = 1/1

ns

Output timing measurement reference level

1.4

V

Output load condition

See Fig. 2

3.3V

1200

Ω

870

Ω

Output

50pF*1

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Vtt = 1.4V

50

Ω

Output

50pF*1

Z0 = 50

Ω

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit

1. The DC/AC Test Output Load of KM432S2030C-6/7 is 30pF.

2. The VDD condition of KM432S2030C-6 is 3.135V~3.6V.

Note :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer. Refer to the following clock unit based AC conversion table

Notes :

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Version

Unit

Note

-6

-7

-8

-10

CLK cycle time

tCC(min)

6

7

8

10

ns

Row active to row active delay

tRRD(min)

12

14

16

20

ns

1

RAS to CAS delay

tRCD(min)

18

20

ns

1

Row precharge time

tRP(min)

18

20

ns

1

Row active time

tRAS(min)

42

49

48

50

ns

1

tRAS(max)

100

us

Row cycle time

tRC(min)

66

67

68

70

ns

1

Last data in to row precharge

tRDL(min)

2

CLK

2,5

Last data in to new col.address delay

tCDL(min)

1

CLK

2

Last data in to burst stop

tBDL(min)

1

CLK

2

Col. address to col. address delay

tCCD(min)

1

CLK

3

Mode Register Set cycle time

tMRS(min)

2

CLK

Number of valid output data

CAS Latency=3

2

ea

4

CAS Latency=2

1

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