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KM681002AI-12 데이터시트(PDF) 2 Page - Samsung semiconductor |
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KM681002AI-12 데이터시트(HTML) 2 Page - Samsung semiconductor |
2 / 9 page KM681002A, KM681002AI CMOS SRAM PRELIMINARY Rev 4.0 - 2 - Ferruary 1998 128K x 8 Bit High-Speed CMOS Static RAM GENERAL DESCRIPTION FEATURES • Fast Access Time 12, 15, 20ns(Max.) • Low Power Dissipation Standby (TTL) : 25mA(Max.) (CMOS) : 8mA(Max.) Operating KM681002A - 12 : 170mA(Max.) KM681002A - 15 : 165mA(Max.) KM681002A - 20 : 160mA(Max.) • Single 5.0V ±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Center Power/Ground Pin Configuration • Standard Pin Configuration KM681002AJ : 32-SOJ-400 KM681002AT: 32-TSOP2-400F KM681002A -12/15/20 Commercial Temp. KM681002AI -12/15/20 Industrial Temp. ORDERING INFORMATION Clk Gen. I/O1~I/O8 CS WE OE FUNCTIONAL BLOCK DIAGRAM Data Cont. Column Select A9 A10 A11 A12 A13 A14 A15 A16 CLK Gen. Pre-Charge Circuit Memory Array 512 Rows 256x8 Columns I/O Circuit PIN FUNCTION Pin Name Pin Function A0 - A16 Address Inputs WE Write Enable CS Chip Select OE Output Enable I/O1 ~ I/O8 Data Inputs/Outputs VCC Power(+5.0V) VSS Ground The KM681002A is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681002A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung ′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM681002A is packaged in a 400mil 32-pin plastic SOJ or TSOP2 forward. PIN CONFIGURATION(Top View) SOJ/ TSOP2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O8 I/O7 Vss Vcc I/O6 I/O5 A12 A11 A10 A9 A8 A0 A1 A2 A3 CS I/O1 I/O2 Vcc Vss I/O3 I/O4 WE A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A8 |
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