AUP

LVC

AUP

AUP

LVC

Static-PowerConsumption

( A)

m

Dynamic-PowerConsumption

(pF)

Single,dual,andtriplegates.

†

3.3-V

Logic

†

3.3-V

Logic

†

0%

20%

40%

60%

80%

100%

0%

20%

40%

60%

80%

100%

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

0

5

10

15

20

25

30

35

40

45

Time(ns)

†

AUP1G04dataatC =15pF.

L

Output

Input

SwitchingCharacteristics

at25MHz

†

SN74AUP1G04

SCES571H – JUNE 2004 – REVISED MARCH 2010

www.ti.com

Figure 1. AUP – The Lowest-Power Family

Figure 2. Excellent Signal Integrity

This single inverter gate performs the Boolean function Y = A.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

preventing damaging current backflow through the device when it is powered down.

ORDERABLE PART

TOP-SIDE

NUMBER

NanoStar™ – WCSP (DSBGA)

Reel of 3000

SN74AUP1G04YFPR

_ _ _ H C _

0.23-mm large bump – YFP

QFN – DRY

Reel of 5000

SN74AUP1G04DRYR

HC

uQFN – DSF

Reel of 5000

SN74AUP1G04DSFR

HC

–40°C to 85°C

SOT (SOT-23) – DBV

Reel of 3000

SN74AUP1G04DBVR

H04_

SOT (SC-70) – DCK

Reel of 3000

SN74AUP1G04DCKR

HC_

SOT (SOT-553) – DRL

Reel of 4000

SN74AUP1G04DRLR

HC_

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3)

DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.

YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

FUNCTION TABLE

INPUT

INPUT

A

B

H

L

L

H

2

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Product Folder Link(s): SN74AUP1G04