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74LVCV2G66DCY66 데이터시트(PDF) 3 Page - NXP Semiconductors |
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3 / 23 page 74LVCV2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 16 June 2010 3 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level. Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8U) 74LVCV2G66 1Z VCC 1Y 1E 2E 2Y GND 2Z 001aai213 1 2 3 4 6 5 8 7 001aai214 74LVCV2G66 Transparent top view 8 7 6 5 1 2 3 4 1Z 1Y 2E GND VCC 1E 2Y 2Z Table 3. Pin description Symbol Pin Description 1Y, 2Y 2, 6 independent input or output 1Z, 2Z 1, 5 independent input or output (overvoltage tolerance) GND 4 ground (0 V) 1E, 2E 7, 3 enable input (active HIGH) VCC 8 supply voltage Table 4: Function table[1] Input nE Switch LOFF-state H ON-state |
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