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SST25WF080-75-4I-SAF 데이터시트(PDF) 4 Page - Silicon Storage Technology, Inc |
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SST25WF080-75-4I-SAF 데이터시트(HTML) 4 Page - Silicon Storage Technology, Inc |
4 / 29 page 4 Advance Information 8Mbit 1.8V SPI Serial Flash SST25WF080 ©2010 Silicon Storage Technology, Inc. S71203-03-000 04/10 MEMORY ORGANIZATION The SST25WF080 SuperFlash memory arrays are orga- nized in uniform 4 KByte sectors with 16 KByte, 32 KByte, and 64 KByte overlay erasable blocks. DEVICE OPERATION The SST25WF080 are accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25WF080 support both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 4, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. FIGURE 4: SPI Protocol 1203 F03.0 MODE 3 SCK SI SO CE# MODE 3 DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MODE 0 MODE 0 HIGH IMPEDANCE MSB MSB |
유사한 부품 번호 - SST25WF080-75-4I-SAF |
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유사한 설명 - SST25WF080-75-4I-SAF |
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