전자부품 데이터시트 검색엔진 |
|
SST39WF1601-70-4I-B3KE 데이터시트(PDF) 2 Page - Silicon Storage Technology, Inc |
|
SST39WF1601-70-4I-B3KE 데이터시트(HTML) 2 Page - Silicon Storage Technology, Inc |
2 / 29 page 2 Data Sheet 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 ©2009 Silicon Storage Technology, Inc. S71297-05-000 11/09 To meet high density, surface mount requirements, the SST39WF1601/1602 are offered in both 48-ball TFBGA and 48-ball WFBGA packages. See Figures 2 and 3 for pin assignments. Device Operation Commands are used to initiate the memory operation func- tions of the device. Commands are written to the device using standard microprocessor write sequences. A com- mand is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39WF1601/1602 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 5 µA. The Auto Low Power mode reduces the typi- cal IDD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. Read The Read operation of the SST39WF1601/1602 is con- trolled by CE# and OE#, both have to be low for the sys- tem to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is dese- lected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4). Word-Program Operation The SST39WF1601/1602 are programmed on a word-by- word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Pro- gram operation, once initiated, will be completed within 40 µs. See Figures 5 and 6 for WE# and CE# controlled Pro- gram operation timing diagrams and Figure 20 for flow- charts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Pro- gram operation, the host is free to perform additional tasks. Any commands issued during the internal Program opera- tion are ignored. During the command sequence, WP# should be statically held high or low. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. The SST39WF1601/1602 offer both Sector- Erase and Block-Erase modes. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block- Erase operation is initiated by executing a six-byte com- mand sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of- Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11 for timing waveforms and Figure 24 for the flowchart. Any commands issued during the Sector- or Block-Erase oper- ation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low. |
유사한 부품 번호 - SST39WF1601-70-4I-B3KE |
|
유사한 설명 - SST39WF1601-70-4I-B3KE |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |