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74AUP1G97GW 데이터시트(PDF) 4 Page - NXP Semiconductors |
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4 / 22 page 74AUP1G97 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 — 10 January 2011 4 of 22 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate 7.1 Logic configurations Table 5. Function selection table Logic function Figure 2-input MUX see Figure 5 2-input AND see Figure 6 2-input OR with one input inverted see Figure 7 2-input NAND with one input inverted see Figure 7 2-input AND with one input inverted see Figure 8 2-input NOR with one input inverted see Figure 8 2-input OR see Figure 9 Inverter see Figure 10 Buffer see Figure 11 Fig 5. 2-input MUX Fig 6. 2-input AND gate 001aae002 1 2 3 6 5 4Y VCC C B A B A C Y 001aae003 1 2 3 6 5 4Y Y VCC C A A C Fig 7. 2-input NAND gate with input A inverted or 2-input OR gate with input C inverted Fig 8. 2-input NOR gate with input B inverted or 2-input AND gate with input C inverted 001aae004 1 2 3 6 5 4Y Y VCC C A C A Y C A 001aae005 1 2 3 6 5 4Y Y VCC C B C B Y C B Fig 9. 2-input OR gate Fig 10. Inverter 001aae006 1 2 3 6 5 4Y Y VCC C B B C 001aae007 1 2 3 6 5 4Y Y C VCC C |
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