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LC72122V 데이터시트(PDF) 10 Page - Sanyo Semicon Device |
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LC72122V 데이터시트(HTML) 10 Page - Sanyo Semicon Device |
10 / 22 page No. 6113-10/22 LC72122V Continued from preceding page. No. Control block/data Description Related data DO pin control data • Data that determines DO pin output DOC0, DOC1, DOC2 The open state is selected following a power-on reset. Note: 1. end-UC: IF counter measurement completion check When end-UC is set and an IF count is started (CTE = 0 → 1), the DO pin automatically goes to the open state. When the IF count measurement completes, the DO pin goes low and the count completion check operation is enabled. The DO pin goes to the open state due to serial data I/O (CE: high). 2. Goes to the open state if the IO pin itself is set to be an output port. Caution: The DO pin always goes to the open state during the data input period (during the period when CE is high in mode IN1 or IN2), regardless of the values of the DO pin control data (DOC0 to DOC2). Also, the DO pin outputs the content of the internal DO serial data in synchronization with the CL pin signal during the data output period (during the period when CE is high in the OUT mode) regardless of the values of the DO pin control data (DOC0 to DOC2). Unlock detection data • Selects the phase error (øE) detection range for PLL lock discrimination. UL0, UL1 When a phase error greater than the specified range occurs, the LC72122V determines that the PLL is unlocked. (*: Don’t care.) Note: When unlocked, the DO pin goes low and the serial data output UL bit is 0. Phase comparator • Phase comparator dead zone control data control data DZ0, DZ1 Dead zone width: DZA < DZB < DZC < DZD Clock time base • An 8 Hz 40% duty clock time base signal can be output from BO1 by setting TBC to 1. TBC (The BO1 data will be ignored.) Charge pump control data • Data that forcibly controls the charge pump output DLC Note: The LC72122V provides a technique for escaping from deadlock by setting Vtune to VCC (deadlock clear circuit). This is used when the circuit is deadlocked due to the VCO oscillator being stopped by the VCO control voltage (Vtune) being 0 V. (6) (7) (8) (9) (10) UL0, UL1, CTE, IOC1, IOC2 DOC0, DOC1, DOC2 BO1 DOC2 DOC1 DOC0 DO pin state 0 0 0 Open 0 0 1 Low when the unlock state is detected 0 1 0 end-UC*1 0 1 1 Open 1 0 0 Open 1 0 1 The IO1 pin state*2 1 1 0 The IO2 pin state*2 1 1 1 Open UL1 UL0 øE detection width Detector output 0 0 Stopped Open 0 1 0 øE is output directly 1 * ±6.67 µs øE is extended by 1 to 2 ms DZ1 DZ0 Dead zone mode 0 0 DZA 0 1 DZB 1 0 DZC 1 1 DZD DLC Charge pump output 0 Normal operation 1 Forced low Continued on next page. |
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