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ISL32490EIBZ 데이터시트(PDF) 9 Page - Intersil Corporation

부품명 ISL32490EIBZ
상세설명  짹60V Fault Protected, 5V, RS-485/RS-422 Transceivers with 짹25V CMR
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
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ISL32490E, ISL32492E, ISL32493E, ISL32495E, ISL32496E, ISL32498E
9
FN7786.0
January 18, 2011
tZL(SHDN)
Receiver Enable from
Shutdown to Output Low
RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8),
(Notes 11, 13)
Full
-
-
2000
ns
RECEIVER SWITCHING CHARACTERISTICS (15Mbps Versions; ISL32496E, ISL32498E)
fMAX
Maximum Data Rate
-25V ≤ VCM ≤ 25V (Figure 7)
Full
15
25
-
Mbps
tPLH, tPHL Receiver Input to Output Delay -25V ≤ VCM ≤ 25V (Figure 7)
Full
-
35
70
ns
tSKD
Receiver Skew |tPLH -tPHL|(Figure 7)
Full
-
4
10
ns
tZL
Receiver Enable to Output
Low
RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8),
(Note 10)
Full
-
-
50
ns
tZH
Receiver Enable to Output
High
RL = 1kΩ, CL = 15pF, SW = GND (Figure 8),
(Note 10)
Full
-
-
50
ns
tLZ
Receiver Disable from Output
Low
RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8)
Full
-
-
50
ns
tHZ
Receiver Disable from Output
High
RL = 1kΩ, CL = 15pF, SW = GND (Figure 8)
Full
-
-
50
ns
tSHDN
Time to Shutdown
(Note 11)
Full
60
160
600
ns
tZH(SHDN) Receiver Enable from
Shutdown to Output High
RL = 1kΩ, CL = 15pF, SW = GND (Figure 8),
(Notes 11, 13)
Full
-
-
2000
ns
tZL(SHDN)
Receiver Enable from
Shutdown to Output Low
RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8),
(Notes 11, 13)
Full
-
-
2000
ns
NOTES:
6. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
7. Supply current specification is valid for loaded drivers when DE = 0V.
8. Applies to peak current. See “Typical Performance Curves VCC = 5V, TA = +25°C; Unless Otherwise Specified.” beginning on page 14 for more
information.
9. Keep RE = 0 to prevent the device from entering SHDN.
10. The RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN.
11. Transceivers are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts are guaranteed not to
enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See “Low Power Shutdown
Mode” on page 13.
12. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN.
13. Set the RE signal high time >600ns to ensure that the device enters SHDN.
14. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design.
15. Tested according to TIA/EIA-485-A, Section 4.2.6 (±80V for 15µs at a 1% duty cycle).
16. See “Caution” statement below the “Latch-up (Tested per JESD78, Level 2, Class A) +125°C” section on page 5.
Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C (Note 6).
Boldface limits apply over the operating temperature range, -40°C to +85°C.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 14)
TYP
MAX
(Note 14)
UNITS


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