전자부품 데이터시트 검색엔진 |
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LC7872E 데이터시트(PDF) 9 Page - Sanyo Semicon Device |
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LC7872E 데이터시트(HTML) 9 Page - Sanyo Semicon Device |
9 / 17 page Pin Functions No. 4868-9/17 LC7872E Pin No. Symbol I/O Function 1 S1 I S1 S2 CD DSP CD DSP selection 0 0 LC7861N/67 2 S2 I 1 0 LC7860K/63 1 1 LC7868/69/681 3 SBCK O Subcode R to W readout clock 4 SFSY I Subcode frame synchronization signal 5 PW I Subcode R to W data 6 SBSY I Subcode block synchronization signal 7 VDD1 — Digital system power supply 8 CE I Serial input or control pin during serial output 9 DO O Serial data output (N-ch open drain) 10 DI I Serial data input 11 CL I Serial data I/O clock 12 MUTE I Control signal that invalidates the subcode data 13 VSS1 — Digital system ground 14 WE O DRAM control 15 RAS O DRAM control 16 A0 O DRAM address 17 A1 O DRAM address 18 A2 O DRAM address 19 A3 O DRAM address 20 A4 O DRAM address 21 A5 O DRAM address 22 A6 O DRAM address 23 A7 O DRAM address 24 DB0 I/O DRAM data 25 CAS O DRAM control 26 DB1 I/O DRAM data 27 OE O DRAM control 28 DB2 I/O DRAM data 29 DB3 I/O DRAM data 30 CB I High: color bar output (pull-down resistor built in) Low: normal mode 31 CDGM O Outputs a high level when a CD-G disk detected 32 TRANS0 O Transparency digital output 33 TRANS1 O Transparency digital output 34 TRANS2 O Transparency digital output 35 TRANS3 O Transparency digital output 36 TRANS4 O Transparency digital output 37 TRANS5 O Transparency digital output 38 VSS2 — Composite video D/A converter ground 39 VDD2 — Composite video D/A converter power supply 40 BIAS O Ripple exclusion capacitor connection 41 VIDEO O Composite video output (8-bit D/A converter output) 42 TEST I Test pin. Must be tied low in normal operation (pull-down resistor built in) 43 LINE I When pin NP2 is high: High: 263H, Low: 262H When pin NP2 is low: High: 312H, Low: 314H 44 FSCIN I Subcarrier clock input (feedback resistor built in) 45 VSYNC O Vertical synchronization signal output 46 TEST1 I Test pin. Must be tied low in normal operation (pull-down resistor built in) 47 YS O Superimposition control output 48 CSYNC O Composite synchronization signal output 49 4FSC2 I Superimposition mode external clock input (feedback resistor built in) 50 EFLG O Error state monitor Continued on next page. |
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